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In Power over Ethernet (POE) systems, it is desired to measure a unique resistance signature at the load to identify that a device is capable of being powered. For instance, it is typically desired to identify a resistive load placed at a Powered Device (PD) end of a cable such as a category 5 type cable. In one known technique, an applied voltage is first measured across the resistive load and then the current flowing therethrough is measured for identifying the value of the resistive load. Thereafter, the value for the resistive load is obtained by dividing the measured values of the applied voltage by the current.
However, if the resistive load is shunted by a large capacitance, then a predefined number of time constants is required as a settling time before making the DC measurements to prevent distortion by the shunt capacitance charging current and allow an accurate resistive load measurement to be performed. As a result of the settling time associated with the shunt capacitance, the time required for the resistive load measurement calculation increases. Additionally, the resistive load may appear in series with a non-linear device, such as a diode, having an offset voltage which must be subtracted to obtain an accurate resistive load measurement. The offset is typically obtained by making measurements at two different terminal voltages and then calculating the difference between the two measurements. Again, time for allowing the line capacitance to settle is required in the resistive load measurement which further increases the resistive measurement time.
As the resistive load is generally placed at the PD end of a long cable, the resistive load measurement is also susceptible to noise pickup from the cable. To minimize the effect of this noise, an averaging technique is utilized in the measurement of the applied voltage and current for obtaining the equivalent DC value of the waveform which adds more time and complexity to the measurement calculation. It is therefore desirable to provide a resistive load measuring system which reduces the time and complexity that are associated with the known systems and methods.
The present invention provides a system for precisely measuring a resistive load embedded in a potentially non-linear and capacitive PD network which eliminates variable voltage from the measurement, decreases the capacitive settling times, and averages out system noise. The present invention is directly applicable to silicon integration and is particularly applicable to Power over Ethernet (POE) systems where the presence of a resistive signature is used to identify that a device is capable of being powered.
According to an embodiment of the present invention, a system for sensing and measuring a resistive load in a non-linear network includes a current and voltage (I-V) controller for receiving control voltages, applying constant load voltages to the resistive load in response to receiving the control voltages, and generating current flow voltages corresponding to current flowing through the resistive load. An integrating analog to digital converter (ADC) circuit receives the generated current flow voltages from the I-V controller and performs measurement cycles thereon. In each of the measurement cycles, one of the current flow voltages is integrated for a fixed time interval to generate an integrated voltage and then the one integrated voltage is de-integrated to generate a digital output value reflecting the magnitude of the current flow voltage.
A control processor is operatively communicative with both the integrating ADC circuit and the I-V controller for controlling the measurements and calculations on the resistive load. During a first measurement cycle, the control processor switches to a first control voltage for input to the I-V controller and obtains a first digital output value from the integrating ADC circuit in response to integrating a first current flow voltage from the I-V controller. After completion of the first measurement cycle, a second measurement cycle is performed wherein the control processor switches to a second control voltage for input to the I-V controller and obtains a second digital output value from the integrating ADC circuit in response to integrating a second current flow voltage from the I-V controller for the fixed time interval. After the second measurement cycle, the control processor calculates the resistive load value based on the difference between the first and second digital output values.
Other aspects, features and advantages of the present invention are disclosed in the detailed description that follows.